1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device comprising a plurality of vertically stacked memory cells.
2. Description of the Related Art
As the density of semiconductor elements increases, the semiconductor elements are being more and more downsized. However, the exposure limit and processing limit in the semiconductor element manufacturing process make it difficult to increase the density in the horizontal direction. Therefore, it is being attempted to increase the density by vertically stacking memory cells.
Even when memory cells can be vertically stacked, however, it is difficult to form contacts electrically connecting peripheral circuits to the memory cells. One possible means for solving this problem is a method that forms a via hole in each of vertically stacked memory cells, and forms a contact in this via hole.
Unfortunately, this method decreases the yield and increases the manufacturing cost because an exposing step, developing step, and processing step must be repeated whenever a contact is formed. In addition, if the number of memory cells to be stacked increases, the number of contacts increases, and the depth of via holes also increases. As a consequence, misalignment of contacts shortcircuits interconnections.
As a related technique of this type (Jpn. Pat. Appln. KOKAI Publication No. 2005-85938), a technique that prevents a write error to an unselected memory cell in a nonvolatile semiconductor memory device comprising vertically stacked memory cells is disclosed.